1) Field of the Invention
The present invention relates to a semiconductor flash memory.
2) Description of the Related Art
In general, when an erase/write operation is repeated frequently in a semiconductor flash memory, application of high voltage for the erase/write operation causes a stress, which degrades transconductance characteristic, gm, of a memory cell. As a result, ON current of the memory cell decreases, and OFF current increases. This phenomenon is referred to as “gm degradation”, which will cause harmful effects on the semiconductor flash memory, such as “a decrease of read speed accompanied with the decrease of the ON current of the memory cell”, and “a decrease of read margin accompanied with the increase of the OFF leak current of unselected memory cells”.
As the ON current decreases, read speed decreases because low ON current of the memory cell is input to a sense amplifier. As the OFF leak current increases, difference between the ON current and the OFF leak current becomes smaller, which makes it difficult to judge “0” or “1” of read data, causing a decrease of the read margin.
A technology is disclosed in, for example, Japanese Patent Application Laid-Open Publication No. 2001-43691, to cope with the problem of gm degradation. In this technology, identical data is written into two memory cells or more, and at read process, true data is obtained by logical addition or majority judgment. In Japanese Patent Application Laid-Open Publication No. 1999-96782, another technology is disclosed in which identical data is written into two memory cells or more, and data is read simultaneously. However, because it is supposed that adjustment of verify threshold value is performed collectively for two memory cells or more, there is a possibility that a difference of the threshold value occurs between memory cells into which data is written.
However, in the conventional technology, one bit data is read by sensing the ON current of one memory cell at a read process of the semiconductor flash memory. Accordingly, when the gm degradation occurs, the read speed decreases. On the other hand, from a user side, there is a demand for an increased number of rewrite guarantee times for complicated applications.
Furthermore, the array of a reference memory cell that generates reference current to judge whether the selected read cell is in a write status or in an erase status is formed on a small block separate from the array of the read cell, and the distance from the sense amplifier to the read cell differs from that of the reference memory cell. As a result, loads of bit lines are different with each other, making the above structure unsuitable for high speed read by the sense amplifier of a differential amplification circuit.
Furthermore, when a write process is performed initially, data is held thereafter in the array of the reference memory cell of a separate block. Therefore, even if the erase/write operation is performed for many times, degradation of the transconductance gm will not occur. In other words, in repetitions of the erase/write operation, differences in characteristics occur between the read cell and the reference memory cell, and threshold voltage difference that should be constant will change, accordingly. From this point of view, the above structure is not suitable for high-speed read of the semiconductor flash memory.
Through repetitions of the read operation or by holding data for a long time, characteristics of both the read cell and the reference memory cell will change just after a write or an erase operation. There will be a cell whose threshold value is higher than read verify voltage, a cell whose threshold value is higher than erase verify voltage, and a cell whose threshold value is higher or lower than the threshold value set in the reference memory cell. The threshold value voltage difference between initially set read cell and reference memory cell will change, and the structure becomes unsuitable for high-speed read.
Furthermore, in the technology specified in FIG. 4 of Japanese Patent Application Laid-Open Publication No. 1999-96782, it is necessary to arrange one word line driver to each word line, therefore, in the advanced ultra fine configuration of memory cells at present, it is almost impossible to contain a word line decoder into the pitch of the word line.